Design of low power high -performance of 2-4 and 4-16 mixed logic line decoders

G Jhansi Rani, M Mahaboob Basha

Abstract


This paper presents a Mixed logic design strategy for line decoders, consolidating transmission entryway logic, pass transistor double esteem logic and static CMOS. Two epic topologies are exhibited for the 2-4 decoder: a 14-transistor topology pointing on limiting transistor tally and power dispersal and a 15-transistor topology pointing on high power-defer execution. Both a typical and a modifying decoder are actualized for each situation, yielding an aggregate of four new designs. Besides, four new 4-16 decoders are designed, by utilizing blended logic 2-4 pre decoders joined with standard CMOS post-decoder. All proposed decoders have full swinging ability and decreased transistor check contrasted with their traditional CMOS partners. At long last, an assortment of relative recreations at the 65 nm demonstrates that the proposed circuits present a noteworthy enhancement in power and postponement, outflanking CMOS in all cases.


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