Design of Nand Gate by Using Dvs and Multitheshold Technique

Y. Narendra, M.Koteswara Rao

Abstract


In advanced and simple circuits, control utilization assumes a critical job in CMOS gadget. Because of scale down innovation in VLSI circuits the edge voltage of transistors lessened however increments in sub threshold spillage current. To decrease the sub threshold spillage current the powerful circuit level procedure is proposed. In this paper, the MTCMOS strategy is proposed which gives fast and low power scattering by keeping up the execution of the circuits. The NAND entryway is structured utilizing DVS and MTCMOS strategy gives slightest power utilization. Every one of the reenactments has been performed on Leather treater EDA Tool adaptation 14.1. The proposed method lessens the power scattering by 30% to 70%.


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