Vlsi Implementation Of 16 × 16-Digit Parallel Multiplier

Y. Srilakshmi, T. Lilly Prasanthi

Abstract


Decimal X × Y multiplication is a complex operation, where intermediate partial products (IPPs) are commonly selected from a set of pre-computed radix-10 X multiples. Some works require only [0, 5] × X via recoding digits of Y to one-hot representation of signed digits in [−5, 5]. This reduces the selection logic at the cost of one extra IPP. Two’s complement signed-digit (TCSD) encoding is often used to represent IPPs, where dynamic negation (via one XOR per bit of X multiples) is required for the recoded digits of Y in [−5, −1]. In this work, despite generation of 17 IPPs, for 16-digit operands, we manage to start the partial product reduction (PPR) with 16 IPPs that enhance the VLSI regularity. Moreover, we expected to save negating XORs via representing pre-computed multiples by sign-magnitude signed-digit (SMSD) encoding. For the first-level PPR, we devise an efficient Ladner Fischer adder, with two SMSD input numbers, whose sum is represented with TCSD encoding. Expected results shows that some performance improvement over previous relevant designs.


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