Design of External Inductor for Improving Performance of Voltage Controlled Dstatcom

D. Ramesh, G.Vishnu Vardhan Reddy, D. Naresh

Abstract


In this Project, a new DSTATCOM topology with reduced dc link voltage is proposed. The distribution static compensator (DSTATCOM) is used for load compensation in power distribution network. In the presence of feeder impedance, the inverter switching distorts both the PCC voltage and the source currents. A new DSTATCOM topology with reduced dc link voltage is proposed. The topology consists of two capacitors: one is in series with the interfacing inductor of the active filter and the other is in shunt with the active filter. The series capacitor enables reduction in dc-link voltage while simultaneously compensating the reactive power required by the load, so as to maintain unity power factor without compromising DSTATCOM performance. The shunt capacitor, along with the state feedback control algorithm, maintains the terminal voltage to the desired value in the presence of feeder impedance with the reduction in dc-link voltage, the average switching frequency of the insulated gate bipolar transistor switches of the DSTATCOM is also reduced. Consequently, the switching losses in the inverter are reduced. Detailed design aspects of the series and shunt capacitors are discussed in this paper. A simulation study of the proposed topology has been carried out using MATLAB/SIMULINK. Finally a fuzzy logic controller is applied for further reduction of harmonics on source side.


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