Design A 8 Bit Fault Tolerant Parallel Ffts Using Parseval Checks

T. Venkata Narayana Reddy, G.V.Ravi Kumar

Abstract


Presently, the circuits of communication and signal processing became more difficult. This is due to the CMOS technology scaling in which more transistors is integrated on a single device. The transistors which are operated with low voltages are known as scaling. These are more liable to the errors caused by the noise and manufacturing variations. Errors cause the reliability risk for advanced electronic circuits. Algorithm Based Fault Tolerance (ABFT) technique is used to utilize the algorithmic properties. FFTs are the major key building blocks in every system. Perseval or sum of square check is one of the techniques which are most extensively used. A technique has been proposed which utilizes this reality to implement fault tolerance on parallel filters. Initially, this technique is applied to secure the FFTs. Therefore, two protection schemes are proposed and evaluated which unify the usage of Error Correction Codes (ECC) and Parceval checks.


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