High Speed Sharing Logic BIST Environment Creation for Testing Operation

K. Satya Manuja

Abstract


hen built-in test generation used for a design that can be partitioned into logic blocks, it is advantageous to identify groups of blocks whose tests have similar characteristics, and use the same built-in test generation logic for the blocks in each group. This project studies this issue for a built -in test generation method that produces functional broadside effects. Functional broadside effects are important for addressing over testing of delay faults as well as avoiding excess power dissipation during test application. The project discusses the design of the test generation logic for a group of logic blocks, and the selection of the groups. Functional broadside tests are two-pattern scan based test that avoid over testing by ensuring that a circuit traverses only reachable states during the functional clock cycles of test. In addition, the power dissipation during the fast functional clock cycles of functional broadside tests does not exceed that possible during functional °operation. On-chip test generation has the added advantage that it reduces test data volume and facilitates at -speed test application. This project shows that on -chip generation of functional broadside tests can be done using a simple and fixed hardware structure, with a small number of parameters that need to be tailored to a given circuit, and can achieve high transition fault coverage for testable circuits. With the proposed on chip test generation method, the circle is used for generating reachable states during test application .

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