Vedic Multiplier based Fault Tolerant FFTs through Verilog HDL

Ganesh Payyavula, Prasad Janga

Abstract


Algorithmic-Based Fault Tolerance (ABFT) technique is used to exploit the algorithmic properties to detect and correct errors. One example is Fast Fourier transforms (FFTs) that is used in spectral analysis in the communication. There are several protection schemes to detect and correct errors in FFTs. Among those, most likely the utilization of the Parseval or add of squares check is that the most generally glorious. The Parseval or sum of square check is the most widely known. It is most common to find several blocks operating in parallel in the modern communication systems. Recently, a method that exploits this truth to implement fault tolerance on parallel filters has been projected. During this temporary, this system is 1st applied to guard FFTs. Then, 2 improved protection schemes that mix the utilization of error correction codes and Parseval checks are projected and evaluated. This project outspread with FFT using Vedic multiplier. Simulation results are observed using Xilinx.


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