Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme

V. Tholkappian, B. Karthick


In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the pulse generation control logic, an AND func- tion, is removed from the critical path to facilitate a faster discharge oper- ation. A simple two-transistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various postlayout simulation results based on UMC CMOS 90-nm technology reveal that the proposed design features the best power-delay-product performance in seven FF designs under com- parison.


Flip-flop, low power, pulse-triggered

Full Text:



  • There are currently no refbacks.

Copyright (c) 2014 V. Tholkappian, B. Karthick

Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.


EduPedia Publications Pvt Ltd, D-351, Prem Nagar-2, Suleman Nagar, Kirari, Nagloi, New Delhi PIN-Code 110086, India Through Phone Call us now: +919958037887 or +919557022047

All published Articles are Open Access at https://edupediapublications.org/journals/

Paper submission: editor@edupediapublications.com or edupediapublications@gmail.com

Editor-in-Chief       editor@edupediapublications.com

Mobile:                  +919557022047 & +919958037887

Websites   https://edupediapublications.org/journals/.

Journals Maintained and Hosted by

EduPedia Publications (P) Ltd in Association with Other Institutional Partners


Pen2Print and IJR are registered trademark of the Edupedia Publications Pvt Ltd.