A High-Throughput VLSI Architecture for SC-FDMA MIMO Detectors



Large-scale multiple-input multiple output is termed to be one of the key technology in future generation multiple cellular systems supporting the 3GPP LTE. LTE includes MIMO technology with orthogonal frequency division-multiple access technology surrounded by the downlink and single carrier-frequency division multiple access (SC-FDMA). This paper introduces a novel low-complexity multiple-input multiple-output (MIMO) detector tailored for single-carrier frequency division-multiple access (SC-FDMA) systems, suitable for efficient hardware implementations. The proposed detector starts with an initial estimate of the transmitted signal based on a minimum mean square error (MMSE) detector. Subsequently, it recognizes less reliable symbols for which more candidates in the constellation are browsed to improve the initial estimate. An efficient high-throughput VLSI architecture is also introduced achieving a superior performance compared to the conventional MMSE detectors.

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